A conventional prior art MOS transistor output buffer circuit 10 is illustrated in FIG. 1. Multiple output buffers of this type may be incorporated, for example, in an octal buffer line driver. The pulldown transistor element is provided by the relatively large current carrying capacity NMOS transistor element N1. The pullup transistor element is provided by relatively large current carrying capacity PMOS transistor element Pl. Output buffer circuit 10 in the example of FIG. 1 is a non-inverting tristate output device, and data signals propagate from the input V.sub.IN to the output V.sub.OUT in the bistate operating mode. The tristate output enable and disable signals are applied at the OE terminal input.
A data signal at the input V.sub.IN passes through two inverting current amplification stages 12,14 and then is applied at the same polarity as the input to NAND gate 15 and NOR gate 16. NAND gate 15 drives pullup transistor element P1. NOR gate 16 drives the pulldown transistor element N1. The second input to each of the gates 15,16 is derived from the OE terminal input.
An output enable signal OE is applied in inverted polarity OE at the tristate OE terminal. This tristate signal passes through first and second inverting current amplification stages 18,20 and is applied at the same polarity as the OE signal to the input of NOR gate 16. The tristate signal also passes through first and second inverting stages of current amplification 18,20 and a third inverter stage 22 before it is applied to the input of NAND gate 15. The tristate signal applied to the input of NAND gate 15 is thus of opposite polarity from the OE signal and is in phase with output enable signal OE.
The logic gate arrangement of the output buffer circuit 10 of FIG. 1 delivers output data signals of logic high and low potential levels at the output V.sub.OUT in phase with data signals at the input V.sub.IN during bistate operation when the output enable signal OE is high (OE low). When the OE signal is low (OE high) during the high impedance third state, both the pullup transistor element P1 and the pulldown transistor element N1 are disabled. The output V.sub.OUT appears as a high impedance to other output buffers on a common bus.
A prior art TTL output device 20 is illustrated in FIG. 2. A pullup transistor element, Darlington amplifier transistor pair Q4,Q4A, sources a relatively large current from the high potential TTL power supply rail V.sub.CC through collector resistor R4 to an output node V.sub.OUT. A relatively large pulldown transistor element Q3 sinks current from the output node V.sub.OUT to the ground or low potential power rail, GND. The phase splitter transistor element Q2 controls the conducting states of the pullup transistor element Darlington pair Q4,Q4A and the pulldown transistor element Q3 in opposite phase in response to logic high and low potential level data signals at the input node V.sub.IN.
The base of phase splitter transistor element Q2 is coupled to the input node V.sub.IN through the input transistor element Q1 which delivers base drive current to phase splitter transistor Q1 from the TTL power supply V.sub.CC through resistor R1 when the input signal at input node V.sub.IN is at the logic high potential level. When a logic low level signal appears at the input node V.sub.IN the phase splitter transistor Q2 is deprived of base drive current. The TTL output gate 20 in the example of FIG. 2 is therefore inverting. A logic high level potential signal at input node V.sub.IN produces a logic low level potential signal at output node V.sub.o and vice versa.
With a high level potential signal at V.sub.IN, phase splitter Q2 conducts current from TTL power supply V.sub.CC through resistor R2. Current is diverted from the base of the Darlington transistor Q4A. Phase splitter transistor Q2 drives the base of the pulldown transistor element Q3. Diode SD2 helps discharge the base of Darlington transistor Q4 during the transition from high to low at the output. With a low level potential signal at V.sub.IN phase splitter transistor Q2 is not conducting, the pulldown transistor element Q3 is deprived of base drive, and current from TTL power supply V.sub.CC through resistor R2 drives the base of the pullup transistor element Q4A. Resistor R3 is the discharge path for the pulldown transistor Q3. A TTL output buffer line driver is typically also constructed as a tristate output device, for example, as described in U.S. Pat. Nos. 4,287,433; 4,255,670; 4,311,927; 4,581,550; 4,661,727; and 4,649,297.
In both MOS and bipolar technology output buffer line drivers, a relatively large current carrying capacity primary pulldown transistor element is coupled at the output for sinking a relatively large discharge current from the output to ground. A relatively large current carrying capacity primary pullup transistor element is coupled at the output for sourcing a relatively large charging current to the output from a power supply. The pulldown transistor element turns on for discharging the output load capacitance and for sinking current from the output to the ground rail GND to effect the transition from logic high to low potential at the output V.sub.OUT. The surge or acceleration of charge develops a voltage across the output ground lead parasitic inductance LG proportional to L di/dt resulting in a positive ground rise in potential or ground bounce in what should be a static low potential power rail. This ground bounce may typically be in the order of 0.5 to 2.5 volts above the external ground 0 volts for circuits with a power source V.sub.CC operating at 5 volts.
The disruptive effects of this noise on the output ground and supply leads include pulsing of noise on input and internal circuit ground and power supply lines; threshold shifts in the reference voltages for high and low potential level data signals causing false data signals; and of particular concern to the present invention, interference with other low or quiet output buffer circuits on a common bus by transfer of ground bounce noise spikes from the ground rail to the output. The disruption of quiet buffer circuit outputs on a common ground bus is a particular problem of MOS output buffer circuits because the NMOS pulldown transistor element N1 provides a highly conductive path from ground rail GND to output V.sub.OUT. For example, a logic low condition output buffer of an octal buffer line driver may receive a voltage rise ground bounce pulse causing a false high data signal. These problems associated with output ground and supply noise are of increased concern in recent integrated circuits that switch higher currents at higher speeds.
While transfer of ground bounce noise spikes from the ground rail GND to the output V.sub.OUT is a particular problem of MOS output buffer circuits, it also occurs in bipolar output devices. The NPN bipolar transistor structure is often accompanied by a parasitic diode coupling between the grounded substrate and the buried collector layer and collector region, providing a conductive path for transfer of ground bounce noise spikes from the ground rail GND to the output V.sub.OUT. Furthermore, base drive current is diverted to the low output during such ground bounce events. Another disadvantage of the bipolar output device is the requirement for quiescent current I.sub.CC for continued functioning of the device even in the logic low potential level output condition.
A BICMOS output drive stage as illustrated in FIG. 3 alleviates some of the problems of the separate MOS or separate bipolar output buffer circuit. In the conventional BICMOS pulldown circuit shown in FIG. 3, the MOS pulldown transistor element NB controls a final bipolar output pulldown transistor element QB. The BICMOS combination eliminates the quiescent base drive current requirement to the bipolar output pulldown transistor element QB so there is no diversion of base drive current to the output V.sub.OUT during a ground bounce event. However, the NMOS transistor element NB and NPN transistor element QB still tend to have parasitic clamp diodes which pass reduced amplitude ground bounce pulses from the ground rail GND to the output V.sub.OUT. Furthermore, the BICMOS circuit of FIG. 3 cannot pull down the output V.sub.OUT below 1V.sub.BE, e.g. approximately 0.6 v-0.8 v.
The phrase "transistor element" is used herein to refer to integrated circuit transistors from different IC technologies including MOS transistors such as NMOS and PMOS transistor elements, and bipolar transistors including, for example, NPN and PNP transistor elements in TTL and ECL circuits. The transistor elements are generically characterized as having a primary current path with primary current path first and second terminal leads or electrodes, and a third control terminal lead or electrode for controlling the conducting state of the primary current path. In the case of an NMOS transistor element, for example, the primary current path first terminal lead is the drain lead, the second terminal lead is the source lead, and the third control terminal lead is the gate lead, etc. In the case of a bipolar NPN transistor element, the primary current path first terminal lead is the collector lead, the second terminal lead is the emitter lead, and the control terminal lead is the base lead, etc. In the case of PMOS and PNP transistor elements, the role of the first and second terminal leads are the inverse from that of the NMOS and NPN transistor elements respectively.